FET driving circuit

ABSTRACT

A FET driving circuit includes: two inputs for inputting a DC voltage; two outputs respectively connected to gate and source electrodes of a FET; a switch; a resonant capacitance connected between both ends of the switch; and an LC resonance circuit connected between the inputs and both ends of the switch. When the two inputs are shorted, frequency characteristics of an impedance of the LC resonance circuit include, in order from a low to a high-frequency side, first to fourth resonant frequencies. The first resonant frequency is higher than a switching frequency of the switch, the second resonant frequency is around double the switching frequency, the fourth resonant frequency is around four times the switching frequency, and the impedance has local maxima at the first resonant frequency and the third resonant frequency and local minima at the second resonant frequency and the fourth resonant frequency.

FIELD OF THE INVENTION

The present invention relates to a FET (Field Effect Transistor) driving circuit that drives a FET used as a switching element, such as a converter, an inverter, or a switching power supply.

DESCRIPTION OF THE RELATED ART

A resonant FET driving circuit is well known as a FET driving circuit for driving a FET (for example, a MOSFET) at a high switching frequency (see Non-Patent Literature 1 (Very-High-Frequency Resonant Boost Converters, IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 6, JUNE 2009, PP 1654-1665) and Patent Literature 1 (Japanese Translation of PCT International Publication No. 2007-501544)).

Non-Patent Literature 1 discloses a self-excited FET driving circuit which, as depicted in FIG. 5 of the cited document, includes a switch element (MOSFET) connected between the gate electrode and the source electrode of the FET to be driven and an LC resonance circuit that is connected to the gate electrode of the FET to be driven and functions as a load network for the switch element. This FET drive circuit is capable of outputting a trapezoidal resonant gate driving voltage to the FET.

Patent Literature 1 discloses a FET driving circuit equipped with an inductor that is connected at a first end to the gate electrode of the FET to be driven, a first switch that is connected between a first end of a power supply that outputs a power supply voltage and a second end of the inductor, a third switch that is connected between the first end of the power supply and the first end of the inductor, a second switch that is connected between the second end of the power supply that is grounded and the second end of the inductor, and a fourth switch that is connected between the second end of the power supply and the first end of the inductor. In this FET driving circuit, by driving the four switches with the timing depicted in FIG. 3 of the cited document, the inductor is precharged, and by doing so, it is possible to charge and discharge the gate capacitance of the FET to be driven at high speed (that is, the gradient is set steeper than the voltage gradient of the gate-source voltage, or in other words, the respective times taken by the voltage to rise and fall are shortened).

SUMMARY OF THE INVENTION

However, since the FET driving circuit in Non-Patent Literature 1 described above is self-excited, there is the problem that the design is complex and a further problem in that the switching frequency fluctuates. On the other hand, although the FET driving circuit according to Patent Literature 1 mentioned above is externally excited and therefore does not have the problems with the FET driving circuit according to Non-Patent Literature 1 described above (the problems of being complex to design and the switching frequency fluctuating), the FET driving circuit according to Patent Literature 1 requires four switches, which increases the cost of circuitry and since dead time needs to be set to prevent cross conduction, it is difficult to increase the operating frequency.

The present invention was conceived in view of the problems described above and has an object of providing a FET driving circuit that is capable of even higher frequency operation by increasing the voltage gradients of rises and falls in the driving waveform (that is, by making the time taken by rises and falls in the driving waveform shorter) which is supplied to the gate electrode of a FET to be driven while avoiding increases in cost and fluctuations in the switching frequency.

To achieve the stated object, a FET driving circuit according to the present invention comprises: two direct current (DC) input terminals that are positive and negative and into which a DC voltage is inputted; two output terminals that are connected to a gate electrode and a source electrode of a FET to be driven; a switch with two ends; a resonant capacitance connected between both ends of the switch; and an LC resonance circuit that is connected between the two DC input terminals and both ends of the switch, wherein a voltage generated across both ends of the switch during a switching operation is outputted across the two output terminals as a driving voltage for the FET, and when looking from both ends of the switch when the two DC input terminals are shorted, frequency characteristics of an impedance of the LC resonance circuit include, in order from a low-frequency side to a high-frequency side, a first resonant frequency, a second resonant frequency, a third resonant frequency, and a fourth resonant frequency, the first resonant frequency is higher than a switching frequency of the switch, the second resonant frequency is a resonant frequency that is around double the switching frequency, the fourth resonant frequency is a resonant frequency that is around four times the switching frequency, and the impedance has local maxima at the first resonant frequency and the third resonant frequency and local minima at the second resonant frequency and the fourth resonant frequency.

Here, the LC resonance circuit internally includes a first inductance, a second inductance, a third inductance, a first capacitance, and a second capacitance, wherein the first inductance, the second inductance, and the third inductance are connected in order in series between one DC input terminal out of the two DC input terminals and one end out of the two ends of the switch, another DC input terminal out of the two DC input terminals is directly connected to another end out of the two ends of the switch, the first capacitance is connected between the other end of the switch and a junction between the first inductance and the second inductance, and the second capacitance is connected in parallel to the second inductance.

Alternatively, the LC resonance circuit internally may include a fourth inductance, a fifth inductance, a sixth inductance, a third capacitance, and a fourth capacitance, wherein the fourth inductance, the fifth inductance, and the sixth inductance are connected in order in series between one DC input terminal out of the two DC input terminals and one end out of the two ends of the switch, another DC input terminal out of the two DC input terminals is directly connected to another end out of the two ends of the switch, the third capacitance is connected between the other end of the switch and a junction between the fourth inductance and the fifth inductance, and the fourth capacitance is connected between the other end of the switch and a junction between the fifth inductance and the sixth inductance.

Alternatively, the LC resonance circuit may internally include a seventh inductance, an eighth inductance, a ninth inductance, a fifth capacitance, and a sixth capacitance, wherein the seventh inductance, the fifth capacitance, and the eighth inductance are connected in order in series between one DC input terminal out of the two DC input terminals and one end out of the two ends of the switch, another DC input terminal out of the two DC input terminals is directly connected to another end out of the two ends of the switch, the ninth inductance is connected in parallel to a series circuit composed of the seventh inductance and the fifth capacitance, and the sixth capacitance is connected between the other end of the switch and a junction between the seventh inductance and the fifth capacitance.

Alternatively, the LC resonance circuit may internally include a tenth inductance, an eleventh inductance, a twelfth inductance, a seventh capacitance, and an eighth capacitance, wherein a series circuit, which is composed of the tenth inductance and the seventh capacitance, and the eleventh inductance are connected in order in series between one DC input terminal out of the two DC input terminals and one end out of the two ends of the switch, another DC input terminal out of the two DC input terminals is directly connected to another end out of the two ends of the switch, the twelfth inductance is connected in parallel to the series circuit, and the eighth capacitance is connected between the other end of the switch and a junction between the series circuit and the eleventh inductance.

In the FET driving circuit according to the present invention, the LC resonance circuit internally includes inductances that are magnetically coupled.

In the FET driving circuit according to the present invention, the switch performs a Class E switching operation.

In the FET driving circuit according to the present invention, a DC-cutting capacitance is connected to at least one of a path that connects one end of the switch and one output terminal out of the two output terminals and a path that connects another end of the switch and another output terminal out of the two output terminals.

Here, the DC-cutting capacitance may be connected to both of the path that connects the one end of the switch and the one output terminal out of the two output terminals and the path that connects the other end of the switch and the other output terminal out of the two output terminals.

In the FET driving circuit according to the present invention, a biasing circuit that applies a DC bias to the driving voltage is connected across the two output terminals.

According to the present invention, it is possible, by repeatedly switching a switch on and off in a FET driving circuit equipped with an LC resonance circuit with impedance characteristics including four resonant frequencies (a first resonant frequency to a fourth resonant frequency), to output a driving voltage for driving the FET to be driven across the output terminals. Here, by using an LC resonance circuit with optimized impedance characteristics, it is possible to attenuate a second harmonic component and a fourth harmonic component of a switching frequency in the voltage applied across both ends of the switch when the switch is off, and by doing so, it is possible to produce a waveform that is closer to a rectangular waveform. In this way, with this FET driving circuit, since it is possible to lower the voltage applied across both ends of the switch, it is possible to use a switch with a low withstand voltage and therefore a low on-resistance, which makes it possible to reduce the loss (conduction loss) of the driving circuit itself. At the same time, since it is possible to reduce the peak value of the gate driving voltage of the FET to be driven, it is possible to maintain a low derating for the gate voltage of the FET to be driven, which makes it possible to improve the reliability of the FET. Also, according to this FET driving circuit, it is possible to significantly shorten the time taken by the voltage applied across both ends of the switch to rise and fall (i.e., to significantly steepen the voltage gradients of rises and falls), which makes it possible to significantly reduce the switching loss of the driving circuit itself. At the same time, it is possible to significantly shorten the time taken by the gate driving voltage of the FET to be driven to rise and fall (i.e., to significantly steepen the voltage gradients of rises and falls), which makes it possible to significantly reduce the switching loss and conduction loss at the FET. Also, according to this FET driving circuit, it is possible to reduce the driving loss due to current resonance between the input inductance and the input capacitance, which is the gate-source characteristics of a FET. Since a single switch is sufficient in this FET driving circuit, compared to a configuration that uses a larger number of switches, it is possible to avoid an increase in the cost of components, an increase in the mounting cost of components, and an increase in the mounting area of components, and to also realize a simplified circuit. Since no dead time is set to prevent cross conduction, it is also possible to drive the FET at even higher frequencies. Since an externally excited configuration is used, it is also possible to avoid fluctuations in the switching frequency. According to this FET driving circuit, since the amplitude of the voltage to drive the FET depends on the DC input voltage, by adjusting the DC input voltage, it is possible to freely adjust the amplitude of the voltage. In particular, when switching operations are performed at high frequency, various adverse effects will occur if the wiring paths of the patterns on which the high-frequency switching current flows are long. However, with a FET driving circuit that includes an LC resonance circuit with the impedance characteristics described above, it is easy to make the wiring paths extremely short and suppress the effects of noise, such as components being affected by noise or conversely emitting noise. By integrating the components, it is possible to suppress differences in the fluctuations in element characteristics, which contributes to making operations more stable. It is also possible to reduce the manufacturing cost, to miniaturize the device, and optimize the operation of the device.

It should be noted that the disclosure of the present invention relates to a content of Japanese Patent Application 2017-124330 that was filed on 26 Jun. 2017 and the entire content of which is herein incorporated by reference.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and features of the present invention will be explained in more detail below with reference to the attached drawings, wherein:

FIG. 1 is a diagram schematically depicting a circuit configuration of a FET driving circuit 1;

FIG. 2 is a diagram useful in explaining the frequency characteristics of the optimized impedance characteristics Z of an LC resonance circuit 4 that include four resonant frequencies;

FIG. 3 is a circuit diagram depicting a first specific example of the LC resonance circuit 4 with the optimized impedance characteristics Z;

FIG. 4 is a circuit diagram depicting a second specific example of the LC resonance circuit 4 with the optimized impedance characteristics Z;

FIG. 5 is a circuit diagram depicting a third specific example of the LC resonance circuit 4 with the optimized impedance characteristics Z;

FIG. 6 is a circuit diagram depicting a fourth specific example of the LC resonance circuit 4 with the optimized impedance characteristics Z;

FIG. 7 is a waveform diagram useful in explaining the operation of a FET driving circuit 1 equipped with the LC resonance circuit 4 in any of FIG. 3 to FIGS. 6; and

FIG. 8 is a schematic diagram useful in explaining a voltage waveform of the voltage V2 in FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Several preferred embodiments of the present invention will now be described. Note that the present invention is not limited to the following embodiments. The component elements described below include equivalent component elements that should be apparent to those of skill in the art, and such component elements may be combined as appropriate.

The embodiments of the present invention will now be described in detail with reference to the drawings. Note that in the description of the drawings, elements that are the same have been assigned the same reference numerals and duplicated description thereof is omitted.

First, the configuration of a FET driving circuit 1 as one example of a FET driving circuit will be described with reference to FIG. 1.

The FET driving circuit 1 includes a pair of direct current (DC) input terminals 2 a and 2 b (hereinafter collectively referred to as the “DC input terminals 2” when no distinction is made), a pair of output terminals 3 a and 3 b (hereinafter collectively referred to as the “output terminals 3” when no distinction is made), an LC resonance circuit 4, a switch 5, a resonant capacitance 6, a DC-cutting capacitance 7 (hereinafter, simply “capacitance 7”), and a biasing circuit 8, and is configured so as to be capable of outputting a driving voltage V4 from the output terminals 3 a and 3 b to a FET (as one example, a MOSFET) 11 to be driven.

More specifically, a DC input voltage V1 is inputted across the pair of DC input terminals 2 a and 2 b with the DC input terminal 2 b connected to a reference potential (in the present embodiment, the common ground G) as the low-potential side. The pulsed driving voltage V4 is outputted across the pair of the output terminals 3 a and 3 b with the output terminal 3 b, which is also connected to the reference potential, as a reference.

The switch 5 is constructed of a MOSFET, a bipolar transistor or the like. In the FET driving circuit 1, due to the switch 5 performing an on/off operation (i.e., a switching operation) in synchronization with a driving signal voltage Vp outputted from a control circuit, not illustrated (i.e., by using an externally-excited configuration), the DC input voltage V1 inputted from the DC input terminals 2 is converted to the driving voltage V4 and outputted from the output terminals 3.

The FET 11 is subject to be driven on/off by the switch 5, and due to the input characteristics of the FET 11, the series circuit, composed of the equivalent of an input inductance and an input capacitance (neither is shown) being present between the gate and the source of the FET 11, is a load that is responsive to the on/off switching of the switch 5. Also, the LC resonance circuit 4 with optimized impedance characteristics Z and the resonant capacitance 6 are loads that are responsive to the on/off switching of the switch 5.

The LC resonance circuit 4 is composed of a two-terminal-pair network (i.e., a four-terminal network) with four external connection terminals (a first connector 4 a, a second connector 4 b, a third connector 4 c, and a fourth connector 4 d). Note that the LC resonance circuit 4 may be a combined resonance-impedance element as a single electronic component that is a three-terminal element or a four-terminal element configured by integrating an inductance and a capacitance that are internally provided.

As one example, in the LC resonance circuit 4, by connecting the first connector 4 a to one DC input terminal (in the present embodiment, the DC input terminal 2 a) out of the pair of DC input terminals 2 a and 2 b, connecting the second connector 4 b to another DC input terminal (in the present embodiment, the DC input terminal 2 b) out of the pair of DC input terminals 2 a and 2 b, connecting the third connector 4 c to one end out of the two ends of the switch 5, and connecting the fourth connector 4 d to the other end out of the two ends of the switch 5, the pair of DC input terminals 2 a and 2 b are connected to both ends of the switch 5. By connecting (or “directly connecting”, that is, connecting directly using a wire, a conductive pattern, or the like) the second connector 4 b and the fourth connector 4 d in the internal circuitry of the LC resonance circuit 4 so that the second connector 4 b and the fourth connector 4 d become the same potential, the connectors 4 b and 4 d are both connected to the common ground G. Accordingly, it is also possible to use a configuration where the connecters 4 b and 4 d are a single connector.

The LC resonance circuit 4 is formed so as to have optimized impedance characteristics Z like those depicted in FIG. 2 as the frequency characteristics of the impedance seen from both ends of the switch 5 (that is, the impedance between the two connectors 4 c and 4 d) when the two DC input terminals 2 a and 2 b are shorted (for example, when the output impedance of a power supply, not illustrated, that outputs the DC input voltage V1 across the DC input terminals 2 a and 2 b is a low impedance, or in other words, when the equivalent of a short circuit is produced between the DC input terminals 2 a and 2 b).

In more detail, as depicted in FIG. 2, these frequency characteristics (or “the optimized impedance characteristics Z”) of the impedance of the LC resonance circuit 4 include, in order from the low-frequency side to the high-frequency side, a first resonant frequency, a second resonant frequency, a third resonant frequency, and a fourth resonant frequency. The first resonant frequency is higher than the switching frequency of the switch 5, the second resonant frequency is around double the switching frequency, and the fourth resonant frequency is around four times the switching frequency. The impedance has local maxima at the first resonant frequency and the third resonant frequency and has local minima at the second resonant frequency and the fourth resonant frequency.

Although a voltage V2 with the same frequency as the switching frequency is generated across both ends of the switch 5 during the off period, the impedance of the LC resonance circuit 4 has local minima at even-numbered multiples of (in the example described above, double and four times) the switching frequency, which means that even-numbered components (in the examples described above, the second harmonic component and the fourth harmonic component) out of the harmonic components that construct the waveform of the voltage V2 generated across both ends of the switch 5 are attenuated by the LC resonance circuit 4. On the other hand, as described above, the LC resonance circuit 4 has local maxima at the first resonant frequency and the third resonant frequency, and due to this, odd-numbered components (mainly the third harmonic component) out of the harmonic components that construct the waveform of the voltage V2 are not attenuated in the same way as the base frequency component (the first harmonic component), and so remain. As a result, as depicted in FIG. 8, compared to a waveform W2 where only the second harmonic component is attenuated (that is, a waveform composed of the base frequency component and the third and fourth harmonic components), the waveform W1 of the voltage V2 whose second harmonic component and fourth harmonic component are attenuated (i.e., a waveform formed of the base frequency component and the third harmonic component) rises and falls more suddenly (i.e., the voltage gradients of the rises and falls are steeper) and has a suppressed amplitude of vibration in a center part, producing a shape that is closer to a rectangular waveform. This means that it is possible to lower the voltage peak value (to around double the DC input voltage V1) and to reduce the time taken to both rise and fall (i.e., to steepen the voltage gradients of both rises and falls). As a result, as depicted in FIGS. 7, the voltage V2 applied across both ends of the switch 5 and the pulsed driving voltage V4 outputted from the output terminals 3 can have lower peak values and steeper rises and falls (i.e., the voltage gradients of rises and falls can be made steeper). Due to this, it is possible to use an element with a low withstand voltage and a low on-resistance as the switch 5, which makes it possible to reduce the conduction loss. The switching loss is also reduced, making it possible to enhance the low-loss effect of the driving circuit as a whole. Meanwhile, it is possible for the FET 11 being driven to maintain a low voltage derating at the gate electrode, and as a result, it is possible to improve the reliability of the FET 11. It is also possible to reduce the switching loss and conduction loss of the FET 11.

Next, specific examples of detailed circuit configurations of the LC resonance circuit 4 with the optimized impedance characteristics Z will be described with reference to FIGS. 3 to 6.

FIG. 3 depicts a first specific example of the LC resonance circuit 4. This LC resonance circuit 4 internally includes a first inductance 411, a second inductance 412, a third inductance 413, a first capacitance 431, and a second capacitance 432. Here, the first inductance 411, the second inductance 412, and the third inductance 413 are connected in that order in series between the first connector 4 a (i.e., the connector that is connected to one DC input terminal 2 a out of the DC input terminals 2 a and 2 b) and the third connector 4 c (i.e., the connector that is connected to one end out of the two ends of the switch 5). The second connector 4 b (i.e., the connector that is connected to the other DC input terminal 2 b out of the DC input terminals 2 a and 2 b) and the fourth connector 4 d (i.e., the connector that is connected to the other end out of the two ends of the switch 5) are directly connected. The first capacitance 431 is connected between the fourth connector 4 d, which is connected as described above to the other end of the switch, and a junction P1 between the first inductance 411 and the second inductance 412. The second capacitance 432 is connected in parallel to the second inductance 412.

FIG. 4 depicts a second specific example of the LC resonance circuit 4. This LC resonance circuit 4 internally includes a fourth inductance 414, a fifth inductance 415, a sixth inductance 416, a third capacitance 433, and a fourth capacitance 434. Here, the fourth inductance 414, the fifth inductance 415, and the sixth inductance 416 are connected in that order in series between the first connector 4 a and the third connector 4 c. The second connector 4 b and the fourth connector 4 d are directly connected. The third capacitance 433 is connected between the fourth connector 4 d and a junction P2 between the fourth inductance 414 and the fifth inductance 415. The fourth capacitance 434 is connected between the fourth connector 4 d and a junction P3 between the fifth inductance 415 and the sixth inductance 416.

FIG. 5 depicts a third specific example of the LC resonance circuit 4. This LC resonance circuit 4 internally includes a seventh inductance 417, an eighth inductance 418, a ninth inductance 419, a fifth capacitance 435, and a sixth capacitance 436. Here, the seventh inductance 417, the fifth capacitance 435, and the eighth inductance 418 are connected in that order in series between the first connector 4 a and the third connector 4 c. The second connector 4 b and the fourth connector 4 d are directly connected. The ninth inductance 419 is connected in parallel to a series circuit composed of the seventh inductance 417 and the fifth capacitance 435. The sixth capacitance 436 is connected between the fourth connector 4 d and a junction P4 between the seventh inductance 417 and the fifth capacitance 435.

FIG. 6 depicts a fourth specific example of the LC resonance circuit 4. This LC resonance circuit 4 internally includes a tenth inductance 420, an eleventh inductance 421, a twelfth inductance 422, a seventh capacitance 437, and an eighth capacitance 438. Here, a series circuit, which is composed of the tenth inductance 420 and the seventh capacitance 437, and the eleventh inductance 421 are connected in that order in series between the first connector 4 a and the third connector 4 c. Note that the series circuit composed of the tenth inductance 420 and the seventh capacitance 437 is not limited to the configuration depicted in FIG. 6 (i.e., a configuration where the tenth inductance 420 is disposed on the first connector 4 a side), and although not illustrated, it should be obvious that the positions of the tenth inductance 420 and the seventh capacitance 437 may be interchanged. The second connector 4 b and the fourth connector 4 d are directly connected. The twelfth inductance 422 is connected in parallel to the series circuit described above. The eighth capacitance 438 is connected between the fourth connector 4 d and a junction P5 between the series circuit described above and the eleventh inductance 421.

The plurality of inductors provided inside the LC resonance circuit 4 may include inductors that are magnetically coupled. As one example, for the example circuit in FIG. 3, at least two out of the first inductance 411, the second inductance 412, and the third inductance 413 may be composed of inductors that are magnetically coupled to each other. By doing so, an LC resonance circuit that has a simple circuit configuration and has four resonant frequencies (the first resonant frequency to the fourth resonant frequency) is realized and at the same time the number of magnetic cores is reduced, which facilitates manufacturing at low cost and optimization. When there are fluctuations in the core characteristics of the inductor cores, it is also possible to suppress differences in fluctuations in the element characteristics of the individual inductors, which contributes to stabilization of operations.

By using this configuration, when the switch 5 is on, a DC current loop composed of the DC input terminal 2 a→the LC resonance circuit 4→the switch 5→the DC input terminal 2 b is formed. On the other hand, when the switch 5 is off, in the LC resonance circuit 4, a current path (current loop) that passes one end of the switch 5 to a capacitance (for example, the first capacitance 431) and then returns to the other end of the switch 5, that is, a current path (i.e., a short current path) that returns to the other end of the switch 5 without passing the DC input terminals 2 is formed for the harmonic components included in the voltage V2, which makes it possible with the FET driving circuit 1 to reduce leakage of harmonic components to the DC input terminals 2.

The resonant capacitance 6 is a resonant capacitance for resonant switching that is connected to both ends of the switch 5. When the switch 5 is a semiconductor element, the resonant capacitance 6 may include the capacitance of junctions provided in the switch 5 (i.e., the output capacitance of the switch 5) and may be composed of only the capacitance of such junctions.

The capacitance 7 is connected on a path that connects both ends of the switch 5 and the output terminals 3 a and 3 b. In the FET driving circuit 1 in FIG. 1, as one example the capacitance 7 is connected on a path that connects one end of the switch 5 and the output terminal 3 a by having one end of the capacitance 7 connected to one end of the switch 5 and the other end of the capacitance 7 connected to the output terminal 3 a, but in place of this configuration, it is also possible to use a configuration where the capacitance 7 is connected on a path that connects the other end of the switch 5 and the output terminal 3 b by having one end of the capacitance 7 connected to the other end of the switch 5 and the other end of the capacitance 7 connected to the output terminal 3 b. Alternatively, the capacitance 7 may be connected to both of these paths. The capacitance 7 has a function (or “DC cutting function”) that removes a DC component included in the voltage V2 that is generated during an off period of the switch 5 at one end of the switch 5 with the other end of the switch 5 (i.e., the common ground G) as a reference and outputs the resulting voltage.

The biasing circuit 8 applies a DC voltage (or “DC bias”) V3 to the voltage V2 from which the DC component has been removed at the capacitance 7 as described above to generate the driving voltage V4. By doing so, as depicted in FIG. 7, the driving voltage V4 is generated as a voltage where the zero potential of the voltage V2, from which the DC component has been removed, is shifted by the DC voltage V3. As one example, although the biasing circuit 8 may be configured as depicted in FIG. 1 to include a DC power supply 8 a that outputs the DC voltage V3 and a diode 8 b that supplies the DC voltage V3 to the other end of the capacitance 7, the biasing circuit 8 is not limited to this configuration. Although the DC voltage V3 is supplied to the other end of the capacitance 7 in a state where the DC voltage V3 has been reduced by the forward voltage of the diode 8 b, for ease of understanding, this forward voltage is ignored in the present embodiment (i.e., the forward voltage is assumed to be zero).

Next, with reference to a steady-state operation waveform diagram given in FIG. 7, the fundamental operation of the FET driving circuit 1 depicted in FIG. 1 will be described in detail for the operation waveforms in each period for a case where the LC resonance circuit 4 has the optimized impedance characteristics Z with four resonant frequencies (i.e., the first resonant frequency to the fourth resonant frequency) depicted in FIG. 2.

Out of the operation waveforms in each period, the operations in the period from time t0 to time t1 are described first. At time t=t0, a driving signal voltage Vp outputted from a control circuit that performs on/off control of the switch 5 becomes a high level to turn the switch 5 on and this high level is maintained until time t=t1. Accordingly, in the period from time t0 to time t1, the switch 5 is on, the voltage V2 applied across both ends of the switch 5 is zero, and a current is that flows to the resonant capacitance 6 is zero. Due to the impedance characteristics of the LC resonance circuit 4 that has the optimized impedance characteristics Z and the gate-source characteristics of the FET 11 to be driven, the current is that flows in the switch 5 jumps from zero to a negative value and then gradually rises via a negative resonant peak (i.e., a local minimum value). Also, since the current i1 that flows to the LC resonance circuit 4 with the optimized impedance characteristics Z as the input current is a resonant current, the current has negative and positive maximum values (peak values) during this period. Meanwhile, the current i4 that flows to the gate electrode of the FET 11 during this period rises from a negative peak value and after this is clipped to zero and maintains this zero value until time t=t1.

Next, the operation in the period from time t1 to time t2 in FIG. 7 will be described. The driving signal voltage Vp applied to the switch 5 at time t=t1 becomes the low level to turn the switch 5 off, with this low level being maintained until time t=t2. Accordingly, the switch 5 is off from the time t1 to the time t2, and due to the impedance characteristics of the LC resonance circuit 4 that has the optimized impedance characteristics Z and the gate-source characteristics of the FET 11, the voltage V2 applied across both ends of the switch 5 from immediately after the switch 5 is turned off resonates and rises from zero with a steep gradient to an amplitude voltage that is around double the DC input voltage V1 (i.e., rises in a short time), passes five resonant peaks (a first resonant peak that is a local maximum, a second resonant peak that is a local minimum, and a third resonant peak that is a local maximum, a fourth resonant peak that is a local minimum, and a fifth resonant peak that is a local maximum) and then falls with a steep gradient (i.e., falls in a short time) to return to zero at time t=t2, so that the derivative with respect to time (i.e., the rate of change in voltage with respect to time) also becomes zero. In other words, the switch 5 performs a Class E switching operation with high efficiency.

By turning off the switch 5 in this period, the current is that flowed in the switch 5 until this time becomes zero and there is a switch to the current ic that flows in the resonant capacitance 6. Here, the current i1 that flows as the input current to the LC resonance circuit 4 has a maximum value at time t=1 and after this reaches a minimum value at time t2 via four resonant peaks (i.e., a first negative resonant peak that is a local minimum, a second positive resonant peak that is a local maximum, a third negative resonant peak that is a local minimum, and a fourth positive resonant peak that is a local maximum). On the other hand, the current i4 that flows to the gate electrode of the FET 11 rises and resonates immediately after reaching the zero value at time t=t1 and then reaches a minimum value at time t=t2 via three resonant peaks (a first resonant peak that is a local maximum, a second resonant peak that is a local minimum, and a third resonant peak that is a local maximum). Accordingly, a current that is the difference between the current i1 and the current i4 flows to the resonant capacitance 6 as the current ic.

Also during the period from time t0 to time t2, the voltage V2 applied to both ends of the switch 5 with the voltage waveform described above has its DC component removed by the capacitance 7, is biased by the biasing circuit 8 adding the DC voltage V3, and is then outputted across the gate and source electrodes of the FET 11 via the output terminals 3 a and 3 b as the driving voltage V4.

The operation in the following period from time t2 to time t3 in FIG. 7 is the same as the operation in the period from time t0 to time t1 described earlier, and the operation in the next following period from time t3 to time t4 is the same as the operation in the period from time t1 to time t2 described earlier. That is, the operation during the period from time t0 to time t2 is repeated during the following periods. Note that although an example where the on time and off time of the driving signal voltage Vp used for on/off control of the switch 5 are equal has been described above, when the on time and the off time of the switch 5 differ, there are cases where the operation voltages and operation current peak times of the various components will also differ.

In this way, with the FET driving circuit 1 that is equipped with the LC resonance circuit 4 that has the optimized impedance characteristics Z with four resonant frequencies (the first resonant frequency to the fourth resonant frequency), by repeatedly turning the switch 5 on and off by outputting the driving signal voltage Vp to the switch 5, it is possible to output the driving voltage V4 to the gate electrode of the FET 11 with the potential of the source electrode of the FET 11 to be driven as a reference. Here, by using the LC resonance circuit 4 with the optimized impedance characteristics Z, it is possible to attenuate the second harmonic component and the fourth harmonic component of the switching frequency in the voltage V2 applied across both ends of the switch 5 when the switch 5 is off, and by doing so, it is possible to produce a waveform that is closer to a rectangular waveform (i.e., a waveform that is closer to a rectangular waveform than a waveform where only the second harmonic component is attenuated). In this way, with the FET driving circuit 1, since it is possible to lower the peak value of the voltage V2 applied to both ends of the switch 5, it is possible to use a switch with a low withstand voltage and therefore a low on-resistance, which makes it possible to significantly reduce the conduction loss and enhance the low loss effect. Also, since it is possible to reduce the peak value of the voltage V2 and in turn the driving voltage V4, it is possible to maintain a low derating for the gate voltage of the FET 11 to be driven, which makes it possible to improve the reliability of the FET 11. Also, according to the FET driving circuit 1, it is possible to shorten the time taken by the voltage V2 to rise and fall, and in turn to further shorten the time taken by the driving voltage V4 to rise and fall (i.e., to further steepen the voltage gradients of rises and falls). By doing so, it is possible to significantly reduce the switching loss at the switch 5, as well as the switching loss and conduction loss at the FET 11 to be driven (i.e., to drive the FET 11 to be driven with a significantly low loss). According to the FET driving circuit 1, since a single component, the switch 5, is sufficient for the switching, compared to a configuration that uses a larger number of switches, it is possible to avoid an increase in the cost of components, an increase in the mounting cost of components, and an increase in the mounting area of components, and to also realize a simplified circuit. Also since no dead time is set to prevent cross conduction, it is possible to drive the FET at even higher frequencies. By using an externally excited configuration, it is also possible to avoid fluctuations in the switching frequency.

According to the FET driving circuit 1 that includes the LC resonance circuit 4 with the optimized impedance characteristics Z that include the four resonant frequencies described above, it is possible with the LC resonance circuit 4 to set the amplitude of the voltage V2 applied to both ends of the switch 5 to around double the DC input voltage V1, so that by changing the DC input voltage V1, it is possible to easily adjust the amplitude of the driving voltage V4 to a suitable amplitude for the FET 11 to be driven. Also, due to the amplitude of the voltage V2 being suppressed to around double the DC input voltage V1, it is possible to lower the withstand voltage of the switch 5, which makes it possible to select a switch with a low on-resistance as the switch 5. As a result, it is possible to achieve a reduction in the conduction loss (or “on loss”) of the switch 5 and to further increase the low loss effect. Also, by using the LC resonance circuit 4 with the optimized impedance characteristics Z, it becomes easier to optimize high-frequency switching operations.

Also, according to the FET driving circuits 1 described above, by using a configuration where the DC component of the voltage V2 is removed at the capacitance 7 and the driving voltage V4 is generated based on the voltage V2 from which the DC component has been removed, the driving voltage V4 that is a negative voltage is applied (outputted) to the gate electrode of the FET 11 with the potential of the source electrode of the FET 11 as a reference, which means that it is possible to switch the FET 11 to the off state more reliably and faster. Note that it should be obvious that it is also possible to use a configuration where the voltage V2 is outputted as it is to the FET 11 as the driving voltage V4 without using the capacitance 7 and the biasing circuit 8.

Also, according to the FET driving circuits 1 described above, by including the biasing circuit 8 and adding the DC voltage V3 from the biasing circuit 8 to the voltage V2, from which the DC component was removed at the capacitance 7, to generate the driving voltage V4, it is possible to apply a driving voltage V4 to the gate of the FET 11 that is split between the positive direction (during an on period) and the negative direction (during an off period). Also, using the voltage value (DC bias value) of the DC voltage V3, it is possible to freely adjust the level at which the voltage is split between positive and negative.

Note that although the FET driving circuit 1 described above is configured so that the DC component of the voltage V2 is removed by connecting the capacitance 7 between one end of the switch 5 and the output terminal 3 a or between the other end of the switch 5 and the output terminal 3 b, it is also possible to use a configuration where the capacitance 7 is connected between both of between one end of the switch 5 and the output terminal 3 a and between the other end of the switch 5 and the output terminal 3 b. With this configuration, it becomes possible to isolate (in DC terms) the potentials of the switch 5 and the potentials of the output terminals 3 a and 3 b, so that although not illustrated, it is possible for example to generate and output a driving voltage V4 that is isolated (in DC terms) to drive a high-potential-side FET out of two FET that are connected in series (i.e., two FET connected in series with the source electrode of the high-potential-side FET connected to the drain electrode of the low-potential-side FET).

Moreover, the invention encompasses any possible combination of some or all of the various embodiments and the modification examples described herein and incorporated herein.

It is possible to achieve at least the following configurations from the above-described example embodiments and the modification examples of the disclosure.

-   (1) A FET driving circuit comprising:

two direct current (DC) input terminals that are positive and negative and into which a DC voltage is inputted;

two output terminals that are connected to a gate electrode and a source electrode of a FET to be driven;

a switch with two ends;

a resonant capacitance connected between both ends of the switch; and

an LC resonance circuit that is connected between the two DC input terminals and both ends of the switch,

wherein a voltage generated across both ends of the switch during a switching operation is outputted across the two output terminals as a driving voltage for the FET, and

when looking from both ends of the switch when the two DC input terminals are shorted, frequency characteristics of an impedance of the LC resonance circuit include, in order from a low-frequency side to a high-frequency side, a first resonant frequency, a second resonant frequency, a third resonant frequency, and a fourth resonant frequency, the first resonant frequency is higher than a switching frequency of the switch, the second resonant frequency is a resonant frequency that is around double the switching frequency, the fourth resonant frequency is a resonant frequency that is around four times the switching frequency, and the impedance has local maxima at the first resonant frequency and the third resonant frequency and local minima at the second resonant frequency and the fourth resonant frequency.

-   (2) The FET driving circuit according to (1),

wherein the LC resonance circuit internally includes a first inductance, a second inductance, a third inductance, a first capacitance, and a second capacitance,

the first inductance, the second inductance, and the third inductance are connected in order in series between one DC input terminal out of the two DC input terminals and one end out of the two ends of the switch,

another DC input terminal out of the two DC input terminals is directly connected to another end out of the two ends of the switch,

the first capacitance is connected between the other end of the switch and a junction between the first inductance and the second inductance, and

the second capacitance is connected in parallel to the second inductance.

-   (3) The FET driving circuit according to (1),

wherein the LC resonance circuit internally includes a fourth inductance, a fifth inductance, a sixth inductance, a third capacitance, and a fourth capacitance,

the fourth inductance, the fifth inductance, and the sixth inductance are connected in order in series between one DC input terminal out of the two DC input terminals and one end out of the two ends of the switch,

another DC input terminal out of the two DC input terminals is directly connected to another end out of the two ends of the switch,

the third capacitance is connected between the other end of the switch and a junction between the fourth inductance and the fifth inductance, and

the fourth capacitance is connected between the other end of the switch and a junction between the fifth inductance and the sixth inductance.

-   (4) The FET driving circuit according to (1),

wherein the LC resonance circuit internally includes a seventh inductance, an eighth inductance, a ninth inductance, a fifth capacitance, and a sixth capacitance,

the seventh inductance, the fifth capacitance, and the eighth inductance are connected in order in series between one DC input terminal out of the two DC input terminals and one end out of the two ends of the switch,

another DC input terminal out of the two DC input terminals is directly connected to another end out of the two ends of the switch,

the ninth inductance is connected in parallel to a series circuit composed of the seventh inductance and the fifth capacitance, and

the sixth capacitance is connected between the other end of the switch and a junction between the seventh inductance and the fifth capacitance.

-   (5) The FET driving circuit according to (1),

wherein the LC resonance circuit internally includes a tenth inductance, an eleventh inductance, a twelfth inductance, a seventh capacitance, and an eighth capacitance,

a series circuit, which is composed of the tenth inductance and the seventh capacitance, and the eleventh inductance are connected in order in series between one DC input terminal out of the two DC input terminals and one end out of the two ends of the switch,

another DC input terminal out of the two DC input terminals is directly connected to another end out of the two ends of the switch,

the twelfth inductance is connected in parallel to the series circuit, and

the eighth capacitance is connected between the other end of the switch and a junction between the series circuit and the eleventh inductance.

-   (6) The FET driving circuit according to any one of (1) to (5),

wherein the LC resonance circuit internally includes inductances that are magnetically coupled.

-   (7) The FET driving circuit according to any one of (1) to (6),     wherein the switch performs a Class E switching operation. -   (8) The FET driving circuit according to any one of (1) to (7),

wherein a DC-cutting capacitance is connected to at least one of a path that connects one end of the switch and one output terminal out of the two output terminals and a path that connects another end of the switch and another output terminal out of the two output terminals.

-   (9) The FET driving circuit according to (8),

wherein the DC-cutting capacitance is connected to both of the path that connects the one end of the switch and the one output terminal out of the two output terminals and the path that connects the other end of the switch and the other output terminal out of the two output terminals.

-   (10) The FET driving circuit according to (8) or (9),

wherein a biasing circuit that applies a DC bias to the driving voltage is connected across the two output terminals. 

What is claimed is:
 1. A FET driving circuit comprising: two direct current (DC) input terminals that are positive and negative and into which a DC voltage is inputted; two output terminals that are connected to a gate electrode and a source electrode of a FET to be driven; a switch with two ends; a resonant capacitance connected between both ends of the switch; and an LC resonance circuit that is connected between the two DC input terminals and both ends of the switch, wherein a voltage generated across both ends of the switch during a switching operation is outputted across the two output terminals as a driving voltage for the FET, and when looking from both ends of the switch when the two DC input terminals are shorted, frequency characteristics of an impedance of the LC resonance circuit include, in order from a low-frequency side to a high-frequency side, a first resonant frequency, a second resonant frequency, a third resonant frequency, and a fourth resonant frequency, the first resonant frequency is higher than a switching frequency of the switch, the second resonant frequency is a resonant frequency that is around double the switching frequency, the fourth resonant frequency is a resonant frequency that is around four times the switching frequency, and the impedance has local maxima at the first resonant frequency and the third resonant frequency and local minima at the second resonant frequency and the fourth resonant frequency.
 2. The FET driving circuit according to claim 1, wherein the LC resonance circuit internally includes a first inductance, a second inductance, a third inductance, a first capacitance, and a second capacitance, the first inductance, the second inductance, and the third inductance are connected in order in series between one DC input terminal out of the two DC input terminals and one end out of the two ends of the switch, another DC input terminal out of the two DC input terminals is directly connected to another end out of the two ends of the switch, the first capacitance is connected between the other end of the switch and a junction between the first inductance and the second inductance, and the second capacitance is connected in parallel to the second inductance.
 3. The FET driving circuit according to claim 1, wherein the LC resonance circuit internally includes a fourth inductance, a fifth inductance, a sixth inductance, a third capacitance, and a fourth capacitance, the fourth inductance, the fifth inductance, and the sixth inductance are connected in order in series between one DC input terminal out of the two DC input terminals and one end out of the two ends of the switch, another DC input terminal out of the two DC input terminals is directly connected to another end out of the two ends of the switch, the third capacitance is connected between the other end of the switch and a junction between the fourth inductance and the fifth inductance, and the fourth capacitance is connected between the other end of the switch and a junction between the fifth inductance and the sixth inductance.
 4. The FET driving circuit according to claim 1, wherein the LC resonance circuit internally includes a seventh inductance, an eighth inductance, a ninth inductance, a fifth capacitance, and a sixth capacitance, the seventh inductance, the fifth capacitance, and the eighth inductance are connected in order in series between one DC input terminal out of the two DC input terminals and one end out of the two ends of the switch, another DC input terminal out of the two DC input terminals is directly connected to another end out of the two ends of the switch, the ninth inductance is connected in parallel to a series circuit composed of the seventh inductance and the fifth capacitance, and the sixth capacitance is connected between the other end of the switch and a junction between the seventh inductance and the fifth capacitance.
 5. The FET driving circuit according to claim 1, wherein the LC resonance circuit internally includes a tenth inductance, an eleventh inductance, a twelfth inductance, a seventh capacitance, and an eighth capacitance, a series circuit, which is composed of the tenth inductance and the seventh capacitance, and the eleventh inductance are connected in order in series between one DC input terminal out of the two DC input terminals and one end out of the two ends of the switch, another DC input terminal out of the two DC input terminals is directly connected to another end out of the two ends of the switch, the twelfth inductance is connected in parallel to the series circuit, and the eighth capacitance is connected between the other end of the switch and a junction between the series circuit and the eleventh inductance.
 6. The FET driving circuit according to claim 1, wherein the LC resonance circuit internally includes inductances that are magnetically coupled.
 7. The FET driving circuit according to claim 1, wherein the switch performs a Class E switching operation.
 8. The FET driving circuit according to claim 1, wherein a DC-cutting capacitance is connected to at least one of a path that connects one end of the switch and one output terminal out of the two output terminals and a path that connects another end of the switch and another output terminal out of the two output terminals.
 9. The FET driving circuit according to claim 8, wherein the DC-cutting capacitance is connected to both of the path that connects the one end of the switch and the one output terminal out of the two output terminals and the path that connects the other end of the switch and the other output terminal out of the two output terminals.
 10. The FET driving circuit according to claim 8, wherein a biasing circuit that applies a DC bias to the driving voltage is connected across the two output terminals.
 11. The FET driving circuit according to claim 9, wherein a biasing circuit that applies a DC bias to the driving voltage is connected across the two output terminals. 